Fault detection is included in circuits to detect error conditions occurring within the circuit. Typical error conditions include unintended short circuits and open circuits. In an exemplary circuit, an amplifier and driver output stage are used to provide drive signals to a remote load via a cable. If the cable becomes shorted to a power supply of the amplifier or to ground, an over-current condition results at the driver output stage. If the cable open circuits, such as a broken or severed cable, the controlled driver current can not be supplied to the load, which results in a driver stage output voltage approaching the supply voltage, in which case the controlling signal will be lost.
A conventional approach for implementing fault detection is to sense the high output current for short circuit conditions, and to sense the output voltage for open circuit conditions. FIG. 1 illustrates a schematic diagram of a conventional driver circuit having fault detection and current limiting functionality. The driver circuit is configured to deliver a driving signal (Vout) to a load, for example a remotely connected sensor. A differential voltage is input to a transconductance amplifier (gm amplifier) 2, which outputs a current proportional to the input voltage. The amplifier output is coupled to a driver circuit having a first transistor T1 coupled to a second transistor T2. In some embodiments, the transistor T1 and the transistor T2 are each metal-oxide-semiconductor field-effect transistors (MOSFETs). In the configuration shown in FIG. 1, the transistor T1 is a p-channel MOSFET, and the transistor T2 is a n-channel MOSFET. It is understood that other types and configurations of transistors can be used. A first output of the amplifier 2 is coupled to a gate of the first transistor T1. A second output of the amplifier 2 is coupled to a gate of the second transistor T2. A bias circuit 4 couples a supply voltage VDD to the first output of the amplifier 2 and to the gate of the transistor T1. A bias circuit 6 couples the second output of the amplifier 2 and the gate of the transistor T2 to ground. A load capacitor Cload is coupled to a drain of the transistor T1 and to a drain of the transistor T2. An output voltage Vout across the load capacitor Cload is used to drive a load.
Short circuit detection is built into the circuit of FIG. 1. A current limiting circuit limits the current through the output driver circuit when a short circuit condition is detected. The current limiting circuit is implemented as a feedback loop including the feedback circuit 8 and the sense resistor Rsense. The feedback circuit 8 measures a voltage Vs at the source of the transistor T1. The current Is through the transistor T1 is determined according to the measured voltage Vs and the known value of the sense resistor Rsense. The feedback circuit 8 compares the determined current Is to an input reference current value Iref. If the current Is reaches the reference current value Iref, then an over-current condition is determined to exist. In response to the over-current condition, the feedback circuit 8 outputs a control current to the gate of the transistor T1 that limits the current Is to a maximum current, such as the reference current value Iref. In other words, the feedback circuit 8 controls the current Is so as not to exceed some predetermined value.
Ideally, the current limiting circuit is designed to detect a short circuit condition at the output of the driver circuit, for example at Vout, and limit the current Is to some over-current value in response to the short circuit. The short circuit may be a short to ground or a short to the supply voltage VDD. Left unresolved, a short circuit results in increasing current Is until breakdown occurs. Determining the over-current condition as described above is intended as a means for identifying a short circuit at the driver circuit output. In addition to limiting the current Is, an over-current flag is output by the feedback circuit 8. However, even if there is not a short-circuit, certain conditions exist that lead to a false short circuit determination made by the feedback circuit 8, referred to as a false short. When a false short is determined, the feedback circuit 8 inappropriately limits the current Is and sends out an over-current flag.
One such condition results from the circuit's inability to differentiate between a real short circuit condition and a normal heavy slewing condition that occurs when charging the load capacitor Cload to the output voltage Vout. The slewing current that charges the load capacitor Cload may be determined as an over-current condition, which causes the slewing current to be limited to the short circuit limit current and an over-current flag to be generated. This problem is intensified with high capacitive loading, such as capacitive loading up to 100 uF, as a larger load capacitor generates a larger slewing current. By limiting the slewing current to the short circuit limit current, the settling time of the circuit is increased. As such, false shorts may result from normal slewing conditions, or the charging of a large load capacitor. The circuit can not differentiate whether the over-current condition is due to the normal slewing condition, the charging of a large load capacitor, or due to an actual short circuit.
Open circuit detection is also built into the circuit of FIG. 1. An open circuit condition may result in the driver circuit losing the control signal. During an open circuit condition, zero current Is flows, and there is no voltage drop across the resistor Rsense. As such, the sensed voltage Vs is the same as the supply voltage VDD. The feedback circuit 8 measures the sensed voltage Vs and if the sensed voltage Vs is equal to the signal voltage VDD, then an open circuit condition is determined and an open circuit error flag is generated. Alternatively, instead of determining if the sensed voltage Vs is equal to the supply voltage VDD, a reference threshold voltage Vthres can be input to the feedback circuit 8, and the sensed voltage Vs is compared to the threshold voltage Vthres. If the sensed voltage Vs is equal to or greater than the threshold voltage Vthres, then the open circuit error flag is generated.
In general, the fault detection circuit of FIG. 1 inappropriately determines certain short duration events as fault conditions. In particular, during the short duration event of charging the load capacitor, the slewing current is greater than the short circuit limit current and an over-current condition is determined. The fault detection circuit can not differentiate between the normal slewing current when the load capacitor is charging versus an actual short circuit condition. False open circuit conditions may result when the output Vout is dynamically switched to a voltage level that approaches the supply level VDD, which results in a longer time period to discharge the load capacitance to a controlled level. FIG. 2 illustrates a schematic diagram of another conventional driver circuit having fault detection and current limiting functionality. The circuit of FIG. 2 has the same input and driver stages as the circuit of FIG. 1. However, the feedback circuit loop of FIG. 2 has a timer to enable a time delay from the onset of the over-current condition to the actual limiting of the current and generation of the over-current error flag. The feedback circuit of FIG. 2 also enables a time delay from the onset of the open circuit condition to the generation of the open circuit error flag.
In particular, the feedback circuit loop includes current and voltage sensing circuits 10 configured to sense the current Is through the transistor T1 and the voltage Vs. As applied to the short circuit condition, the sensed current is input as an input to current and voltage comparators 12. Although shown in FIG. 2 as a single block, the current and voltage comparators block 12 is representative of all circuitry needed to perform current comparisons and voltage comparisons of various inputs. A reference current Isht is input as another input to the comparators 12. The reference current Isht is the short circuit limit current. The comparators 12 determines if the sensed current has reached the short circuit limit current. If the comparators 12 determine that the sensed current is less than the short circuit limit current, then the comparators 12 output a first signal. In some embodiments, the first signal is a “low” signal, such as zero volts. The first signal is input to a current amplifier 14, a preset timer 16, and a timer logic 18. The first signal indicates that an over-current condition has not been met, and that the current Is does not have to be limited. In response to the first signal, the current amplifier 14 outputs a “low” signal, such as zero amps, to the gate of the transistor T1. Also in response to the first signal, the preset timer 16 and the timer logic 18 are in an “off” state. If the comparators 12 determine that the sensed current is equal to or greater than the short circuit limit current, then the comparators 12 output a second signal. In some embodiments, the second signal is a “high” signal, such as some voltage greater than zero volts. The second signal indicates that an over-current condition exists. In response to the second signal, the current amplifier 14 outputs a “high” signal to the gate of the transistor T1. This high signal at the gate limits the current Is to the short circuit limit current. Also in response to the second signal, the preset timer 16 and the timer logic 18 are turned to an “on” state, which starts the clock on the preset timer 16. The clock continues to count until the comparators 12 determine that the sensed current has dropped below the reference current Isht, at which time the comparators 12 output the first signal, which turns off the preset timer and stops the count. The preset timer 16 is set with a count threshold. If the count on the preset timer 16 reaches the count threshold, a count exceeded signal is sent from the preset timer 16 to the timer logic 18. In response to the count exceeded signal, the timer logic 18 generates an over-current error flag. The circuit shown in FIG. 2 is a portion of the MAX15500 chip manufactured by Maxim Integrated Products®, which is hereby incorporated in its entirety by reference.
The preset timer and timer logic in the circuit of FIG. 2 provides for a time delay for issuing an over-current error flag. The time delay is used to account for a short duration event, such as charging the load capacitor Cload, which causes an increase in the current Is to the short circuit limit current for a short period of time. Although the circuit of FIG. 2 allows for such short duration events before issuing an over-current error flag, the current Is is still limited to the short circuit limit current during this time period.
Open circuit detection is also included in the circuit of FIG. 2. Similarly to the open circuit detection of FIG. 1, the sensing circuits 10 sense the voltage Vs, which is input to the comparators 12, along with a threshold voltage Vthres. If the comparators 12 determine that the sensed voltage Vs is less than the threshold voltage Vthres, then the comparators 12 output a third signal. In some embodiments, the third signal is a “low” signal, such as zero volts. The third signal is input to the preset timer 16 and the timer logic 18. The third signal indicates that an over-voltage condition has not been met, and that an open circuit error flag does not have to be generated. In response to the third signal, the preset timer 16 and the timer logic 18 are in an “off” state. If the comparators 12 determine that the sensed voltage Vs is equal to or greater than the short circuit limit current, then the comparators 12 output a fourth signal. In some embodiments, the fourth signal is a “high” signal, such as some voltage greater than zero volts. The fourth signal indicates that an over-voltage condition exists. In response to the fourth signal, the preset timer 16 and the timer logic 18 are turned to an “on” state, which starts the clock on the preset timer 16. The clock continues to count until the comparators 12 determine that the sensed current has dropped below the threshold voltage Vthres, at which time the comparators 12 output the third signal, which turns off the preset timer and stops the count. The preset timer 16 is set with a voltage count threshold. If the count on the preset timer 16 reaches the voltage count threshold, a voltage count exceeded signal is sent from the preset timer 16 to the timer logic 18. In response to the voltage count exceeded signal, the timer logic 18 generates an open circuit error flag.
In addition to inappropriately determining short circuit conditions, the fault detection circuit of FIG. 1 also inappropriately determines certain conditions as open circuit fault conditions, such as when the output voltage Vout is dynamically switched to a voltage level that approaches the supply voltage VDD, which results in a longer time period to discharge the load capacitor to a controlled level. This can result in a false open circuit error flag. Similarly to the over-current condition, the timer and timer logic in FIG. 2 can be used to delay generation of the open circuit error flag.
In addition to generating false error flags, the fault detection circuits of FIGS. 1 and 2 do not have the ability to boost the slewing current beyond the short circuit limit current. In particular, the slewing current is limited by the short circuit limit current when driving large capacitive loads. This results in slower settling time for the circuit. In some applications, loads coupled to the output capacitor Cload have response time requirements that would be adversely affected by a slower settling time. The settling time of a device is the time elapsed from the application of an ideal instantaneous step input to the time at which the device output enters and remains within a specified error band, usually symmetrical about the final value. Settling time includes a propagation delay plus the time required for the output to slew to the vicinity of the final value, recover from the overload condition associated with slew, and settle to within the specified error. Propagation delay, or gate delay, is the length of time starting from when the input to a logic gate becomes stable and valid, to the time that the output of that logic gate is stable and valid. Systems with energy storage elements cannot respond instantaneously and exhibit transient responses when subjected to inputs or disturbances.
In conventional configurations, due to power consumption requirements of the circuit, a short circuit current limit is set by the system, such as about 10 mA. The short circuit current limit is implemented to prevent over current when a short circuit occurs. In the case where the capacitive loading is about 100 uF and the short circuit current limit is about 10 mA, a slew rate of the load capacitor is limited to a maximum at 1V/10 mS.